General purpose registers or a “register file” are a useful component of a data processing system's processing architecture. For instance, a microprocessor or central processing unit (CPU) of a data processing system retrieves operands from one or more general purpose registers to execute instructions. The results of the executed instructions are then stored back in one of the general purpose registers. This allows the data processing system to execute instructions more efficiently. Many prior microprocessor architectures operate in different processor modes, and generally use general purpose registers designated, e.g., R0 through R15.
Typically, prior microprocessor architectures, which use such general purpose registers, process instructions in a normal user mode and an exception handling mode, such as an interrupt mode. For example, in the interrupt mode, a user application is halted in response to an interrupt to a processor. Furthermore, in the interrupt mode, access to some general purpose registers is performed through a separate memory unit referred to as “banked registers” in order to improve exception handling processing. That is, in the interrupt mode, different registers in a separate memory unit, i.e., banked registers, are accessed than in the normal mode.
FIG. 1 illustrates “banked registers” for a prior art microprocessor architecture. As shown, in normal mode, a microprocessor (not shown) accesses registers R0 through R15 in normal mode general purpose registers 100, whereas, in interrupt mode, the microprocessor accesses only registers R8 through R15 in interrupt mode banked registers 102. In this manner, accessing registers in normal mode and interrupt mode requires access to separate memory units. A disadvantage, however, of using banked registers is that it requires a special type of naming scheme to distinguish between the general purpose registers and banked registers, which increases processing overhead. Furthermore, such a general purpose register or “register file” scheme inefficiently accesses registers by requiring access to separate memory units for different processor modes.
Another disadvantage of using the prior art architecture of banked registers is that it does not provide flexibility and efficiency in accessing registers. In particular, the prior art architecture does not allow for aliasing, which is the ability to arbitrarily use the same register across different processor modes. Additionally, the prior art architecture does not allow for fragmentation in which registers can be located in discontinuous locations in memory for access in different processor modes.
There exists, therefore, a need for improved general purpose registers or register files without using separate memory units for register access in different processor modes.